To borrow a phrase from paleontology, the HPC community has historically evolved in punctuated equilibrium. In the 1970s we transitioned from serial to vector architectures. In the 1980s parallel architectures blossomed, and in the 1990s MIMD systems became the norm for most supercomputer architectures. From the 1990s until today we have been in a period of relative stasis in terms of system balance and tradeoffs. Now we’re entering a new phase of rapid evolutionary change triggered by the quest for exascale despite the end of Dennard scaling. With clock speeds not increasing – in fact sometimes decreasing – the only way to go from petaflops to exaflops is to increase hardware parallelism. Nodes, the building blocks of systems, will have many more cores, more hardware threads, more vector units, and, in some cases, more accelerators or co-processors. Memory hierarchies will be deeper, further complicating the design of application software. To read further, please visit http://www.hpcwire.com/2015/09/14/alcfs-paul-messina-on-the-code-optimization-path-to-exascale/.