HPCwire

Since the first details about the MIC architecture emerged, Intel has continually harkened back to their vision of offering a high degree of parallelism inside a power efficient package that could promise programmability. With the eventual entry of the next generation Xeon Phi hitting the market in years to come with its (still unstated) high number of cores, on-package memory, ability to shape shift from coprocessor to processor along the x86 continuum, many are wondering about what kind of programmatic muscle will be needed to spring from Knights Corner to Knight’s Landing. To read further, please visit http://www.hpcwire.com/2013/12/06/intel-sheds-light-corner-landing-leap/?goback=.gde_4178444_member_5814655065880829952#!.