Intel’s Many Integrated Core (MIC) architecture was designed to accommodate highly-parallel applications, a great many of which rely on the Message Passing Interface (MPI) standard. Applications deployed on Intel Xeon Phi coprocessors may use offload programming, an approach similar to the CUDA framework for general purpose GPU (GPGPU) computing, in which the CPU-based application is equipped with directives that send the compute-intensive parts of the code and related data from the host system memory to the coprocessor. Unlike GPGPUs, though, Xeon Phi coprocessors can operate as independent IP-addressable manycore nodes allowing MPI processes to be run on them without involving the host CPUs. The so-called symmetric clustering model is attractive because it allows for relatively easy porting of CPU-based applications to clusters with manycore computing accelerators. The end-user can speedup HPC applications without having to restructure the code to implement data offload. To read further, please visit http://www.hpcwire.com/2014/03/12/benchmarking-mpi-communication-phi-based-clusters/.