Western Digital today announced that it has kicked off production of the industry’s densest 3D NAND flash chips, which stack 64 layers atop another and enable three bits of data to be stored in each cell. The 3D NAND flash chips are based on a vertical stacking or 3D technology that Western Digital and partner Toshiba call BiCS (Bit Cost Scaling). WD has launched its pilot production of its...
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MSST (2017), as is our custom, will dedicate five days to computer-storage technology, including a day of tutorials, two days of invited papers, two days of peer-reviewed research papers, and a vendor exposition. The conference will be held, once again, on the beautiful campus of Santa Clara University, in the heart of Silicon Valley, May 15-19, 2017. Read more at ...
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Gary Grider, deputy division leader of the High Performance Computing (HPC) Division at Los Alamos National Laboratory, was awarded 2015 Richard P. Feynman Innovation Prize at a ceremony last week for his national leadership in developing cutting-edge HPC strategies and his innovative business partnerships. Grider is a leader in the HPC storage community and holds 12 patents and over 30...
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